Senior Hardware Engineer

Job Title: Senior Hardware Engineer
Pay rate: $66.34/hr.
Location: Palo Alto, CA
Zip Code: 94304
Start Date: Right Away
Keywords: #PaloAltoJobs; #SeniorHardwareEngineerjobs;

Job Description:
In this position within the Autonomy Hardware team, you will validate the automotive SoC solutions, build up validation and benchmark framework to identify gaps and risks at component, module level. You will be collaborating with other cross functional teams in gathering all the test requirements, conducting test sequences and collecting data, and ensuring that the test results meet the performance requirements as specified by the architecture.

Requirements and Responsibility
Familiar with HW IP datasheets and user guides, extract critical information regarding register access sequences, expected operation sequences, and their corresponding results, including Register maps, Timing diagrams, Command sequences
Develop test vectors based on the specifications outlined in the datasheet. Consider valid and invalid input scenarios, edge cases for register settings, timing and sequence requirements; enhance the test vectors by incorporating variations in conditions (temperature, voltage) to ensure robustness.
Conducting tests on hardware platforms. Utilize appropriate lab equipment (oscilloscopes, logic analyzers) for testing. Employ debuggers to monitor register accesses and to trace execution paths during testing.
Gather data from tests, noting any discrepancies from expected outcomes. Perform Function Validation by Assessing whether the observed results align with the expected results from the datasheet/user guides. Perform Failure Analysis and Identify potential root causes for any failures, such as timing issues, incorrect register settings, or environmental factors.
Have a hands-on understanding of protocols like JTAG, SPI, I2C, and UART, focusing on Signal integrity, Communication sequences; Use tools to probe these interfaces and verify correct operation during the bring-up phase.
Utilize oscilloscopes to inspect eye diagrams and other analog characteristics to assess signal integrity of high-speed IOs. Measure jitter, rise/fall times, and overall signal quality to ensure compliance with specifications.
Design and implement simple test fixtures using Reference design kits, cables and connectors to facilitate testing of the hardware IP. Ensure the test fixture can accommodate various configurations to test different scenarios.