Server System Interconnect Architect

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THE ROLE:

As EYPC System Interconnect Architect, you will be working with System Architecture, Design on memory focused technologies, representing in standards body (JEDEC, CXL, UCIE, SNIA, OCP), optimizing technology stack that takes advantage of the cross product of AMD technology ingredients and interconnect and memory technologies. You are the architecture expert with experience delivering interconnect solutions, standards understanding, collaborative in nature, and a desire to take on challenging tasks to completion.

KEY RESPONSIBILITIES:

Interconnect Technology, Architecture and Performance is critical for data center operation. With recent trends, significant innovation is seen in the industry across Interconnect technology revolution/evolution and expansion into memory and accelerator domains. Traditional DRAM based memory solutions are running into cost, performance, thermal and use model challenges. HBM use cases are on the rise and enhancements critical for HPC Applications. Compute Express Link opens the possibility for innovative solutions for memory bandwidth capacity and bandwidth expansion, memory disaggregation and memory centric compute. Interconnect standards are evolving at rapid pace, and significant amount of accelerator development and use cases requires interconnect innovations. Developments are happening in computational storage use models, and composable and heterogeneous systems with CPU/GPU/accelerators/NIC that will materialize in the next 5 years.

PREFERRED EXPERIENCE:

The System Interconnect architect will need a working understanding of overall EPYC system, SOC internal IP blocks, SOC internal architecture, board design, memory, IO interfaces and CXL.

• End to end Technical Point of Contact for Interconnect focused Technology definition EPYC products
• Participate in JEDEC, SNIA, UCIe and CXL on IO focused technology development
• Be the technical expert for Business Unit, System design teams on IO focused technologies
• Optimize the workloads that would benefit from these technologies
• Influence the shaping of future products by significantly contributing to the architecture used across design families. Provide technical expertise for next generation IO, fabric interconnects, Die-Die interconnects and CXL initiatives.
• Create and maintain high quality architectural specifications.
• Engage with customers and partners to navigate through feature priorities and potential roadblocks

ACADEMIC CREDENTIALS:

• Bachelor's Degree (BS) in EE, CE, CS plus a minimum of 7 years of industry experience including at least five years focused on SoC and system debug.
• Master's Degree (MS) preferred

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At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD's Employee Stock Purchase Plan. You'll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.